On December 26, 2024, Nano Labs officially unveiled FPU3.0, an advanced ASIC architecture designed to enhance artificial intelligence (AI) inference performance. Featuring state-of-the-art 3D DRAM stacking technology, FPU3.0 achieves a fivefold improvement in energy efficiency over its predecessor, FPU2.0, setting a new benchmark for energy-efficient and high-performance ASICs.

The FPU series represents Nano Labs' proprietary ASIC chip architecture, optimized for high-bandwidth and high-throughput computing (HTC) applications. Compared to traditional CPUs and GPUs, FPU-based ASIC chips offer significantly lower power consumption and higher computational efficiency for targeted functions or applications. These chips are widely used in AI inference, edge AI computing, 5G data processing, and network acceleration.

The FPU architecture consists of four core modules and IPs: Intelligent NOC (Network-on-Chip), high-bandwidth memory controllers, inter-chip I/O connections, and the FPU core. This modular design provides exceptional flexibility, enabling rapid product iterations by updating the FPU core IP while reusing or upgrading other modules and IPs.

Notably, FPU3.0 incorporates stacked 3D memory with a theoretical bandwidth of 24TB/s and an upgraded Intelligent NOC. The enhanced NOC supports hybrid use of large and small computing cores as well as full-crossbar network buses. With outstanding performance across various domains, FPU3.0 delivers higher performance, lower power consumption, and faster product iteration cycles.

The launch of FPU3.0 marks a significant milestone for Nano Labs in driving innovations in AI and blockchain technologies. It underscores our advanced R&D capabilities and commitment to pioneering industry applications. Moving forward, we remain dedicated to advancing cutting-edge chip architectures, furthering the adoption of AI inference and digital currency technologies, and fostering breakthroughs and transformations across the industry.